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design for test (DFT) structure

Standard

ECSS-Q-ST-60-02C - ASIC and FPGA development (31 July 2008)

Definition

technique used to allow a complex integrated circuit (IC) to be tested

Notes

NOTE This can include any mechanism aimed to provide better observability or commandability of internal nodes of the chip not accessible through primary inputs and outputs.

Relations

ECSS-E-ST-70C — DFT
ECSS-Q-ST-60-02C — DFT
ECSS-E-ST-10-12C — IC
ECSS-E-ST-20-08C Rev. 1 — IC

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