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HDL model

Standard

ECSS-Q-ST-60-02C - ASIC and FPGA development (31 July 2008)

Definition

textual model based on a hardware description language (but not a piece of software in itself) suitable for the behavioural or structural description, simulation and by choosing a suitable level of abstraction for automatic netlist generation

Notes

Relations

ECSS-Q-ST-60-02C — HDL
ECSS-E-ST-40-07C — model
ECSS-S-ST-00-01C — model
ECSS-Q-ST-60-02C — netlist
ECSS-E-ST-40-07C — simulation
ECSS-E-ST-40C — software
ECSS-Q-ST-80C Rev.1 — software

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